The present invention relates to a high-speed integrated semiconductor circuit having logic gates, and, more particularly, to such a circuit which is suitable to a semiconductor device having a memory function. In accordance with one aspect of the present invention, the logic gates can be used for a decoder circuit of a semiconductor device having a memory function.
A decoder circuit which is composed of MOS transistors and in which 8 logic gates have an input gate in common is described in, for example, an article by Katsuro Sasaki et al entitled "A 15-ns 1 Mbit CMOS SRAM" in the IEEE JOURNAL OF SOLID-STATE CIRCUITS, Vol. 23, No. 5, 1988, pp. 1067-1072. An example of such a decoder circuit in which 8 logic gates have an input gate in common is shown in FIG. 1. This circuit represents 8 two-input NAND gates. As can be seen in FIG. 1, the circuit includes 8 first PMOS transistors (PMOS load), 8 first NMOS transistors, and one second NMOS transistor that is common for all of the logic gates.
In FIG. 1, the drain of a first PMOS transistor is connected to the drain of a corresponding first NMOS transistor, and the source of the corresponding first NMOS transistor is connected to the drain of a second NMOS transistor which has an input gate which receives a common input for all of the NAND gates. The second NMOS transistor is represented by COMMON NMOS FOR 8 NANDS in FIG. 1. These three kinds of MOS transistors constitute one NAND gate.
The operational state of each of the two-input NAND gates of FIG. 1 is generally classified into four operational states. If it is assumed that the two input terminals are A and B, when both A and B are at a Low level, the output is at a High level. On the other hand, when A is at a Low level and B is at a High level and when A is at a High level and B is at a Low level, the output is at a High level. It is only when both A and B are at a High level that the output is at a Low level.
If it is assumed that the gate of the first NMOS transistor is the input A and the gate of the second NMOS transistor is the input B, when either A or B is at a Low level, either the first NMOS transistor or the second NMOS transistor is turned off, and the output is at a High level. On the other hand, when both A and B are at a High level, both the first NMOS transistor and the second NMOS transistor are turned on and the output is at a Low level.
When a signal to the input gate B of the second NMOS transistor changes from a High level to a Low level and the output thereby changes from a Low level to a High level, the current flowing out of a first PMOS transistor passes through the corresponding first NMOS transistor in the ON state, charges the source-side junction capacitances of the other first NMOS transistors in the OFF state, and thereafter supplies an output at a High level. Therefore, the period from the time when the input signal is changed to the time when the output signal is changed (operation delay time) is inconveniently long. The number of the logic gates which have the input gate B in common is not limited to 8. Therefore, the operation delay time in such a circuit arrangement would further increase with an increase in the number of the logic gates which have the input gate in common.
The delay time between the instant a signal is input to the input portion of a decoder circuit so as to select one memory cell and the instant a signal is output from the output portion is generally determined by the number of stages of logic gates which constitute the decoder circuit. Therefore, it is necessary to reduce the number of stages of logic gates in order to speed up the decoder circuit.
However, when the number of stages of logic gates is reduced, the fan out of the output portion of the logic gate increases and, hence, the capacitance of the gate which is connected to the output portion increases. Consequently, the delay time of the logic gate and, hence, the delay time of the decoder circuit are rather prolonged.
As a result, a speed-up method by a reduction in the number of stages of logic gates and a speed-up method by a reduction in the number of the fan outs are opposed to one another so that a prominent effect on the speedup of the decoder circuit has not hitherto been achieved.
Rapid progress has recently been made in the high integration of a memory. The progress in the high integration of a memory and the increase in the number of memory cells necessitate an increase in the number of stages in the decoder circuit for selecting a memory cell. The increase in the number of stages is a serious obstacle to the speedup of the decoder circuit of the memory device.
Further, to get a high-speed memory device, the control of the data writing and data reading operations are also important.
As an example of a data reading circuit and a data writing circuit, those discussed in ISSCC, Digest of Technical Papers, pp. 186-187, 1988, are conventionally known. FIG. 2 schematically shows an example of such a reading circuit and data writing circuit in the conventional semiconductor memory.
In FIG. 2, the reference numeral 1 represents a data line load circuit, the symbols D, /D represent a pair of data lines (or pair of complementary data lines), WL a word line, the reference numeral 2 represents a memory cell, 101 (M1) and 102 (M2) writing transfer gates, M3 and M4 reading transfer gates, 3 a two-input NOR gate inputting a column select signal /Yi and a writing control signal /W, 4 a decoder circuit for generating the column select signal /Yi on the basis of addresses A.sub.0 to A.sub.n, 10 a common read line for reading the data out of the memory cell, and 11 a common write line for writing data into the memory cell.
To the common read line 10 and the common write line 11, data lines of a plurality of columns are connected through the reading transfer gates 103 (M3) and 104 (M4) and the writing transfer gates 101 (M1) and 102 (M2), respectively.
The operation of the semiconductor memory in the prior art will be explained in the following.
The operation of reading the data from the memory cell is carried out by raising the word line WL so as to read the data held by the memory cell 2 in the form of a potential difference produced on the pair of data lines D, /D. In this case, since the process is in a reading cycle, the writing control signal /W is High and the column select signal /Yi is Low because it has been selected. Therefore, the writing transfer gates 101 (M1) and 102 (M2) are turned OFF and the reading transfer gates 103 (M3) and 104 (M4) are turned ON, so that the potential difference produced on the pair of data lines D, /D is transmitted to the common read line 10 and read out.
On the other hand, at the time of a data writing operation, since both the writing control signal /W and the column select signal /Yi are Low, all of the writing transfer gates 101 (M1) and 102 (M2) and the reading transfer gates 103 (M3) and 104 (M4) are turned ON. The data written on the common write line 11 is transmitted to the pair of data lines D, /D through the writing transfer gates 101 (M1) and 102 (M2) and written into the memory cell of the selected word line WL. The written data is also transmitted from the data lines to the common read line 10 through the reading transfer gates 103 (M3) and 104 (M4).
In the conventional semiconductor memory, the operations of reading data from the memory cell 2 and writing data into the memory cell 2 are executed in the above-described way. In the semiconductor memory in the prior art having the above-described structure of FIG. 2, the common read line 10 is charged and discharged during every data writing operation for the memory cell. Since the common read line is heavily loaded because a plurality of columns are connected thereto, the necessity of charge and discharge during every data writing operation for the memory cell disadvantageously requires a long time for writing.
When the data writing into the memory cell is finished, it is necessary to recover the potential of the data line from the potential at the time of writing to the potential at the time of reading in order to prevent false data from being written into the memory cell or to prevent the delay in the reading time immediately after the writing. In the prior art, it is necessary to recover the potential of the common read line as well as the potential of the data lines, so that much time is required for recovery, which is a serious problem.
Since the increase in the capacity of a semiconductor memory leads to the increase in the load of the common read line, such a problem is serious because of the recent requirements for a larger capacity of a semiconductor memory and a higher access speed. This problem is also contrary to the demand for a lower power dissipation.